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PE4306
Product Specification
Figure 14. Pin Configuration (Top View)
Table 3. Absolute Maximum Ratings
Symbol
V DD
Parameter/Conditions
Power supply voltage
Min
-0.3
Max
4.0
Units
V
C16
1
15
C8
V I
Voltage on any DC input
-0.3
V DD +
0.3
V
RF1
Data
Clock
2
3
4
20-lead
QFN
4x4 mm
Exposed Solder Pad
14
13
12
RF2
P/S
Vss/GND
T ST
P IN
V ESD
Storage temperature range
Input power (50 ? )
ESD voltage (Human Body
Model)
-65
150
+30
500
°C
dBm
V
LE
5
11
GND
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be restricted to
the limits in the Operating Ranges table. Operation
between operating range maximum and absolute
maximum for extended periods may reduce reliability.
Table 2. Pin Descriptions
Table 4. Operating Ranges
Pin No.
1
Pin
Name
C16
Description
Attenuation control bit, 16 dB (Note 4)
Parameter
V DD Power Supply
Voltage
Min
2.7
Typ
3.0
Max
3.3
Units
V
2
3
4
5
6
7
8
RF1
Data
Clock
LE
V DD
PUP1
PUP2
RF port (Note 1)
Serial interface data input (Note 4)
Serial interface clock input
Latch Enable input (Note 2)
Power supply pin
Power-up selection bit
Power-up selection bit
I DD Power Supply
Current
Digital Input High
Digital Input Low
Digital Input Leakage
Input Power
0.7xV DD
100
0.3xV DD
1
+24
μ A
V
V
μ A
dBm
9
V DD
Power supply pin
Temperature range
-40
85
°C
10
11
12
13
14
15
16
17
18
19
GND
GND
V ss /GND
P/S
RF2
C8
C4
C2
GND
C1
Ground connection
Ground connection
Negative supply voltage or GND connection
(Note 3)
Parallel/Serial mode select
RF port (Note 1)
Attenuation control bit, 8 dB
Attenuation control bit, 4 dB
Attenuation control bit, 2 dB
Ground connection
Attenuation control bit, 1 dB
Exposed Solder Pad Connection
The exposed solder pad on the bottom of the package
must be grounded for proper device operation.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS ? device, observe the
same precautions that you would use with other ESD-
sensitive devices. Although this device contains
circuitry to protect it from damage due to ESD,
precautions should be taken to avoid exceeding the
rate specified in Table 3 .
20 N/C No connect. Can be connected to any bias
Paddle GND Ground for proper operation
Notes: 1. Both RF ports must be held at 0 V DC or DC blocked with an external
series capacitor
2. Latch Enable (LE) has an internal 100 k ? resistor to V DD
3. Connect pin 12 to GND to enable internal negative voltage generator.
Connect pin 12 to V SS (-V DD ) to bypass and disable internal negative
voltage generator
4. Place a 10 k ? resistor in series, as close to pin as possible to avoid
frequency resonance. See “Resistor on Pin 1 & 3” paragraph
Moisture Sensitivity Level
The Moisture Sensitivity Level rating for the 5x5 mm QFN
package is MSL1.
Document No. DOC-30007-2 │ www.psemi.com
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS ?
devices are immune to latch-up.
Switching Frequency
The PE4306 has a maximum 25 kHz switching rate.
Resistor on Pin 1 & 3
A 10 k ? resistor on the inputs to Pin 1 & 3 (see
Figure 16 ) will eliminate package resonance between
the RF input pin and the two digital inputs. Specified
attenuation error versus frequency performance is
dependent upon this condition.
?2003-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 11
Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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